The present invention relates to an amplification type solid-state imaging device for amplifying and fetching a signal charge obtained with the photoelectric conversion circuit.
In recent years, as a solid-state imaging device suitable for the application to a video camera, an electronic still camera and the like, development of a CMOS solid-state image sensor is actively being made at various places. The CMOS solid-state image sensor has a structure for amplifying and fetching a signal obtained with the photoelectric conversion circuit for each cell in a MOS transistor. Specifically, the solid-state imaging sensor is an amplification type solid-state imaging sensor in which the inside of pixel is allowed to be provided with an amplification function by reading a signal charge generated by the photoelectric conversion circuit into the detection portion for detecting the electric load and amplifying the potential of this detection portion with an amplification transistor inside of the pixel. Since such amplification type solid-state imaging device is highly sensitive and suitable for a reduction of a pixel size by an increase in the number of pixels and reduction of the image size, so that the amplification type CMOS image sensor is more and more expected along with a low consumption electric power.
Here, FIG. 13 shows a circuit diagram of a conventional amplification type CMOS image sensor. In FIG. 13, a pickup region is arranged and formed in such a manner that one pixel unit of a unit cell is arranged in two-dimension matrix-like manner. Furthermore, each of the unit cells is formed of, for example, four transistors Ta, Tb, Tc and Td, and one photodiode PD. That is, each unit cell comprises a photodiode PD in which a ground potential is supplied to an anode side, a reading transistor Td having one side connected to a cathode side of the photodiode PD, an amplification transistor Tb having a gate connected to the other side of the reading transistor Td, a vertical selection transistor (a row selection transistor) Ta having one side connected to one side of the amplification transistor Tb, and a reset transistor Tc having one side connected to the gate of the amplification transistor Tb.
Furthermore, on a pickup region, there are formed a reading line 4 commonly connected to a gate of each reading transistor of a unit cell on the same line, a vertical selection line 6 commonly connected to a gate of each vertical selection transistor Ta of the unit cell on the same line, and a reset line 7 commonly connected to a gate of each reset transistor Tc of the unit cell on the same line corresponding to each pixel row. Furthermore, on the pickup region, there are formed a vertical signal line VLIN commonly connected to the other end side of each amplification transistor Tb of the unit cell on the same row, and a power source line 9 commonly connected to the other end side of each reset transistor Tc of the unit cell on the same line and the other end side of each vertical selection transistor Ta.
Outside of one end side of the pickup region, a plurality of load transistors TL's connected respectively between each one end side of the vertical signal line VLIN and the ground potential is arranged in a horizontal direction. On the other hand, outside of the other end sides of the pickup region, for example, a noise canceller circuit formed of, for example, two transistors TSH and TCLP and two capacitors Cc and Ct are formed is arranged in a horizontal direction for each of the pixel column. Furthermore, a horizontal selection transistor TH is connected respectively to each of the other end sides of the vertical selection signal line VLIN via these noise canceller circuits.
Furthermore, the horizontal signal line HLIN is commonly connected on each of the other ends of the horizontal selection transistor TH while a horizontal reset transistor (not shown) and an output amplification circuit AMP are connected to this horizontal signal line HLIN. Incidentally, the noise canceller circuit as described above comprises a sample holding transistor TSH having one end side connected to the other end side of the vertical signal line respectively, a coupling capacitor Cc having one end side connected to the other end side of the sample holding transistor TSH, an electric charge accumulation capacitor Ct connected between the other end side of the coupling capacitor Cc and the ground potential, and a potential clamp transistor TCLP connected to these two capacitors Cc and Ct. One end of the horizontal transistor TH is connected to the connection node of two capacitors Cc and Ct here.
Furthermore, outside of the pickup region, a vertical shift register 2 for selecting and controlling in a scanning manner a plurality of vertical selection lines 6 of the pickup region, a pulse selector 2a for driving in a scanning manner the vertical selection line 6 on each line of the pickup region, and a horizontal shift register 3 for driving in a scanning manner the horizontal selection transistor TH. Furthermore, a timing generation circuit 10 for generating each kind of pulse signal on the basis of the external input pulse signal and supplying the signal to a pulse sector 2a, a horizontal shift register 3 and a noise canceller circuit or the like, and a bias generation circuit 11 for generating a predetermined bias potential supplied to one end or the like of the potential clamp transistor TCLP of the noise canceller circuit is arranged outside of the pickup region.
FIG. 14 is a timing waveform diagram showing one example of an operation of a CMOS image sensor shown in FIG. 13. Next, by referring to FIG. 14, an operation of a conventional CMOS transistor will be explained.
A signal charge generated by photo-electrically converting incident light to each photodiode PD is accumulated in the photodiode PD. At the time of reading the signal charge accumulated in the photodiode PD from the unit cell for a desired one line portion in a horizontal blanking period, the vertical selection transistor Ta for one line portion is turned on by activating a signal (φADRESi (i= . . . , n, n+1) pulse) of the vertical selection line 6 on the line to be selected in synchronization with the vertical selection pulse signal φADRES in order to select each of the vertical selection lines 6. With respect to the unit cell for one line portion selected in this manner, a source follower circuit is operated which comprises a load transistor TL and an amplification circuit Tb to which a power source potential (for example, 3.3V) is supplied via the vertical selection transistor Ta.
Next in the selected unit cell for one line portion, the gate voltage of the amplification transistor Tb is reset to a reference voltage by activating a signal (φRESETi pulse) of the reset line 7 so as to be synchronized with the reset pulse signal φRESET with the result that the reference voltage is output to the vertical signal line VLIN for a definite period. However, a variation is present in the gate potential of the amplification transistor Tb of the unit cell for one line portion reset here with the result that the reset potential of the vertical signal line VLIN on the other end side becomes uneven.
Then, in order to eliminate the unevenness of the potential of each vertical signal line VLIN, a drive signal (φSH pulse) of the sample holding transistor TSH in the noise canceller is activated in advance. Furthermore, after the reference voltage is output to the vertical signal line VLIN, the drive signal (φCLP pulse) of the potential clamp transistor TCLP is activated for one definite time thereby setting the reference voltage to the connection node of the two capacitors Cc and Ct of the noise canceller circuit.
Next, after a signal of the reset line 7 is inactivated, the reading line 4 for a predetermined line is selected in synchronization with the reading pulse signal φREAD is selected, and the signal (φRREADi pulse) is activated with the result that the reading transistor Td is turned on, and the accumulation electric load of the photodiode PD is read to the gate of the amplification transistor Tb thereby changing the gate potential. The amplification transistor Tb outputs a signal voltage which corresponds to the change quantity of the gate potential to the corresponding vertical signal line VLIN and the noise canceller circuit.
After that, by turning off the φSH pulse in the noise canceller circuit, a signal component corresponding to a difference portion between the output reference voltage and the signal voltage, namely the signal voltage in which noise is cancelled is accumulated in the capacitor Ct for the electric charge accumulation until the corresponding horizontal selection transistor TH is activated. On the other hand, the pickup region and the noise canceller circuit are electrically separated by inactivating the signal of the vertical selection line 6, to turn off and control the vertical selection transistor Ta, and render the unit cell non-selective.
Subsequently, in the horizontal effective scanning period, after resetting by a horizontal reset signal HRS from the timing generation circuit 10, a shift operation of the horizontal shift register 3 is conducted in synchronization with a timing signal HCK and a drive signal (φH pulse) of the horizontal selection transistor TH is subsequently activated so that the horizontal selection transistor TH is subsequently turned on. In this manner, a connection node of the two capacitors Cc and Ct in the noise canceller circuit, namely, a signal voltage of the signal retention node is subsequently read to the horizontal signal line HLIN followed by being amplified with the output amplification circuit AMP to be output thereafter. Incidentally, the noise canceling operation described above is conducted for each of the reading operation of one horizontal line.
Generally, there is a tendency that the solid-state imaging device such as the CMOS image sensor or the like is used indoors and outdoors, or under various external light such as daylight and midnight. Consequently, there are many cases in which the exposure time is adjusted by controlling the electric charge accumulation time in the photodiode in accordance with a change in the external light or the like, and an operation of an electronic shutter operation is required for setting the sensitivity to an optimal state.
Here, FIG. 15 shows a timing waveform diagram of a vertical shift register in the conventional CMOS image sensor described above. An operation of the conventional CMOS image sensor will be further explained. Incidentally, in FIG. 15, there is shown a case in which the CMOS image sensor is operated in a 30 Hz VGA method of one field= 1/30 Hz.
The φVR of 30 Hz and φHP of 15.7 Hz which are external input pulse signal are formed with a buffer circuit not shown to be input into the vertical shift register in the field cycle and the horizontal cycle respectively. The vertical shift register conducts the shift operation with the pulse signal φHP after clearing all the register output to set the register output to “L” level in the period in which the input of the φVR is on the “L” level thereby subsequently setting the output pulse signal ROi (i= . . . , n, n+1) to the “H” level to input the signal ROi to the pulse selector. The pulse selector activates a signal (φADESi pulse) of the vertical selection signal with respect to each selection line, a signal (φRESETi pulse) of the reset line, and a signal (φREADi pulse) of the reading line to scan the line to be selected.
In this manner, in the CMOS image sensor shown in FIG. 13, each output pulse ROi of the vertical shift register 2 for selecting and controlling a specific line to be selected in one field period is output only once. That is, the photodiode PD discharges an accumulation electric load only once to one field, and the operation of the electronic shutter cannot be conducted for adjusting exposure time by controlling the electric accumulation time of the photodiode.
On the other hand, in the case where, in addition to the vertical shift register for outputting an output pulse signal ROi described above, the vertical shift register for the electronic shutter is provided for selecting and controlling each pixel row prior to this vertical shift register; the signal accumulation time of the photodiode of each pixel row can be controlled on the basis of each output pulse signal from these two vertical shift register with the result that the operation of the electronic shutter is made possible. Here, FIG. 16 shows a circuit diagram of an amplification type CMOS image sensor in which the operation of the electronic shutter is made possible. FIG. 17 shows a timing waveform diagram of the vertical shift register.
In FIG. 16, to the vertical shift register 20 for the electronic shutter, the φES of 30 Hz and the φHP of 15.7 Hz which are external input pulses are input in the field cycle and in the horizontal cycle respectively. Upon receipt of the φES of 30 Hz and the φHP of 15.7 Hz, the vertical shift register 20 for the electronic shutter all clears the register output in the period in which the input of the pulse signal φES is set to a “L” level thereby setting the signal to the “L” level. After that, the shift operation is conducted with the pulse signal φHP to subsequently set the output pulse signal ESi (i= . . . , n, n+1) to input the signal to the pulse selector 2a. 
The pulse selector 2a scans the pixel row of the pickup region so as to activate the signal (φRESETi pulse) of the reset line and the signal (φREADi pulse) of the reading line with respect to the pixel row in which the output pulse signal ROi and ESi from two vertical shift registers 2 and 20 are set to an “H” level. However, with respect to the signal (φADRESi pulse) of the vertical selection line, only the selection object line whose output pulse signal ROi from the reading vertical shift register 2 is set to an “H” level is activated and scanned.
In this manner, as shown in FIG. 17, the signal (φREADi pulse) of the reading line in each pixel row is activated twice within one field period with two vertical shift registers. That is, the signal accumulation timing and the signal reading timing can be set corresponding respectively to the output pulse signals ROi and ESi from the vertical shift register for the electronic shutter and from the vertical shift register for the reading vertical shift register with the result that the electronic shutter can be operated wherein the electronic accumulation time is controlled with the photodiode.
However, in this CMOS image sensor, there is a problem in that the electric charge accumulation time in the photodiode PD at the time of the operation of the electronic shutter can be controlled only in one H (horizontal cycle) unit. This results from the fact that a drive signal is output from the pulse selector 2a to the reading line 4 in synchronization with the reading pulse signal φREAD supplied from the timing generation circuit 10a both in the case of the signal accumulation timing and in the case of the signal reading timing. Here, FIG. 18 shows the timing waveform diagram of the pulse selector 2a. Hereinbelow, by referring to FIG. 18, the problem as described above will be further explained.
As shown in FIG. 18, the drive signal (φREADi (i= . . . , n, n+1) pulse) output twice to the reading line in each pixel row stands in the relation of same phase in the horizontal cycle in any case, as a result from the fact that the timing generation circuit is synchronized with the reading pulse signal φREAD generated in the horizontal blanking period. On the other hand, as apparent from FIG. 17, the selection control of each pixel row by two vertical shift registers is such that after a reset operation is conducted by using as a trigger the pulse signal φVR supplied in the field cycle with respect to the vertical shift register for reading, the pixel row is subsequently selected on the basis of the pulse signal φHP supplied in the horizontal cycle. Furthermore, the vertical shift register for the electronic shutter is reset by using different external input pulse signal φES supplied in the field cycle as a trigger prior to the reading shift register followed by subsequently conducting the selection operation of the pixel row on the basis of the pulse signal φHP supplied in the horizontal cycle thereafter.
Consequently, a gap between the drive signals (φREADi (i= . . . , n, n+1) pulse) output twice to the reading line at each pixel row is determined by multiplying a difference in the operation timing between the two vertical shift registers by using the horizontal cycle as a unit. For example, in the cases shown in FIGS. 17 and 18, the operation by the vertical shift register for the electronic shutter is advanced for one horizontal cycle, namely one pixel row portion with respect to the reading vertical shift register for the electronic shutter, and the pulse selector outputs the drive signal φREADi having the same phase between continuous horizontal periods to the reading line of each pixel row twice on the basis of the output pulse signals ROi and ESi from the two vertical shift registers. At this time, the electric charge accumulation time corresponding to the difference between the signal accumulation timing in the photodiode and the signal reading timing is 1H (horizontal cycle). In the same manner, when the operation by the vertical shift register for the electronic shutter is advanced for m pixel rows (m is an integer) with respect to the vertical shift register for reading, the electric charge accumulation time of the photodiode at each pixel row becomes m×H.
As described above, in the CMOS image sensor shown in FIG. 16, the electronic shutter can be conducted wherein the electric charge accumulation time of the photodiode can be controlled in the unit of 1H (horizontal cycle). However, with the amplification-type solid-state imaging device such as the CMOS image sensor or the like, it is assumed that the apparatus is used in the environment such as outdoors at daytime or the like in which the incident light quantity is extremely large. In order to obtain a favorable image at all times without fear that the high luminance side is not clipped under such circumstances, it is desired that a high speed electronic shutter is realized in which the electric charge accumulation time of the photodiode is decreased to 1H (horizontal cycle) or less.